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perf(mapreduce): vectorized SIMD.jl loads for stride-1 by_block redution - #105

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perf(mapreduce): vectorized SIMD.jl loads for stride-1 by_block redution#105
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@shreyas-omkar shreyas-omkar commented Jul 29, 2026

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Add _mapreduce_nd_by_block_contiguous!, a vectorized variant of the stride-1 by_block reduction

CUDA: RTX 5080

reduce_size vector GB/s scalar GB/s Δ
256 257 255 +1%
512 466 380 +23%
1024 674 468 +44%
4096 687 549 +25%
16384 565 567 tie

AMD RDNA4: RX 9060 XT (gfx1200)

reduce_size vector scalar Δ
256 166 173 −4%
512 277 232 +19%
1024 280 273 +3%
4096 283 281 tie
16384 281 277 +1%

POCL: CPU (AMD Ryzen 7 5700)

reduce_size vector scalar Δ
256 6 5 +20%
512 11 8 +37%
1024 17 14 +21%
4096 21 18 +17%
16384 18 18 tie

oneAPI: Intel Iris Xe

reduce_size vector scalar Δ
256 23 21 +10%
512 32 31 +3%
1024 32 30 +7%
4096 32 27 +19%
16384 26 26 tie

…tion

Add _mapreduce_nd_by_block_contiguous!, a vectorized variant of the stride-1
by_block reduction: each thread pulls W = 16/sizeof(T) contiguous elements
through one 128-bit aligned SIMD.vloada (Vec4 for 4-byte, Vec2 for 8-byte),
lowering to ld.global.v4/v2 on CUDA and global_load_dwordx4 on AMDGPU. Host
gates on stride-1, 4-/8-byte primitive T, and 16-byte-aligned rows; every other
shape/type/layout keeps the scalar by_block path. Correct and faster across
CUDA, AMDGPU, POCL and oneAPI (up to +44% vs scalar on RTX 5080).

Co-Authored-By: Claude Opus 4.8 <[email protected]>
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